FALL IDF: Intel's new chips to run slow, run cool
The new architecture that will grace Intel Corp.’s processors starting in the second half of 2006 borrows many of the design philosophies that made its Pentium M processors a success, Intel executives said Tuesday.
In a rare show of restraint, Intel is not labeling its new architecture with a carefully selected code name. The company wants users to focus on the processors and systems they power, not the brains behind the product, said Intel President and Chief Executive Officer Paul Otellini in a question and answer session following his keynote address at the Intel Developer Forum. He confirmed Intel’s plans to release new dual-core chips for desktops, notebooks and servers based on a common power-saving architecture during his keynote.
The new architecture carries forward some of the technologies found within the Pentium 4’s Netburst architecture, such as 64-bit technology and virtualization features, said Stephen Smith, vice president in Intel’s Digital Enterprise Group and general manager of desktop platforms. However, the design laid out by Intel has much more in common with the company’s Pentium M processor and its focus on saving power, analysts said. It will appear along with the introduction of the Merom processor for notebooks, the Conroe processor for desktops and the Woodcrest processor for servers in the second half of 2006.
The Pentium 4 Netburst products were designed to reach ever faster clock speeds, which was thought to be the most easily understood aspect of processor performance during the design of that product. In order to achieve these speeds, Intel lengthened the pipeline of the processor to 31 stages, almost three times the length of the pipeline in its Pentium III processor.
A processor’s pipeline can be thought of as a series of steps needed to process data. Data is moved into the first stage of a pipeline, processed, and then sent to the next stage. At the same time, new data is brought into the first stage, a process that is repeated on down the pipeline.
Processors with short pipelines do more work in each individual stage of the pipeline in order to produce the end result. This means that they run slower than processors with longer pipelines that only work on a small piece of data in each stage. Those chips, like the Pentium 4, must run very fast in order to get the same amount of work done as a chip with a shorter pipeline.
Hitting those speeds wasn’t a problem for Intel until about 2003. The smaller transistors that accompanied the introduction of the 90-nanometer processing technology for the first time caused a serious power leakage problem, which was exacerbated by the fact that high-frequency processors use a great deal of power.
Intel’s new architecture dials down the power and the clock speed by using only 14 stages to process data, Smith said. Much like the Pentium M processor, this means that the new chips will do more work per stage and can therefore run at slower clock speeds, he said.
Merom and the other new chips can also issue, or start processing, four instructions per clock cycle, Smith said. This is a significant improvement that allows the chip to do even more work per cycle than the Pentium M predecessor, said Nathan Brookwood, principal analyst with Insight 64 in Saratoga, Calif..
Another notable improvement in the company’s new design is the ability of its memory caches to share data. This was first designed into the Yonah dual-core mobile processor that is scheduled to be released in the first quarter of next year, but will be extended to all chips starting next year.
Cache memory stores frequently used instructions close to the processor, where they can be accessed much more quickly than if they are stored in the system’s memory. With Intel’s first dual-core chips, if one processor core needs information that is stored in the cache located adjacent to the other core, it has to request the data by going off the chip through its front-side bus connection to memory. Basically, that’s a waste of time.
Shared caches can exchange data without having to leave the chip, which significantly improves performance. Intel’s new architecture is flexible enough to allow the company to make chips with different cache sizes for different implementations in desktops or notebooks, Smith said.
One glaring issue with Intel’s processor designs left unaddressed by the new architecture is the company’s bus technology used to connect the processor to memory. This vital link is seen by many analysts as overwhelmed by the processing requirements of dual-core processors. The issue isn’t that those processors won’t function properly, but that they are failing to reach their full potential.
Intel views the bus design of its chips as a separate issue from the architecture used to build them, said Dadi Perlmutter, vice president and general manager of Intel’s Mobility Group. He wouldn’t comment on any plans that Intel might have to introduce an integrated memory controller like the one found on rival Advanced Micro Devices Inc.’s Opteron and Athlon 64 chips.
Intel engineers have admitted that the company needs to integrate the memory controller at some point in order to improve the performance of this link, but the company has not said when exactly it plans to do that. Analysts speculate that Intel could do this in 2007, when it introduces new chipset technology for servers that will allow its Itanium and Xeon processors to use the same chipsets.
The shared caches buy Intel some time to get a better memory bus design in place, but “it’s a stopgap solution” until they do so, said Jim McGregor, principal analyst with In-Stat.