Three unlikely bedfellows have joined forces to halve the size of the technology used to make NAND flash chips and microprocessors in an effort to vastly increase the density and capacity of solid-state drives (SSDs) and create faster CPUs that use less power.
According to a Reuters report, Intel, Toshiba and Samsung have entered into a joint development agreement to reduce the size of NAND flash memory circuitry from the 20 nanometer (nm) sizes only recently adopted for manufacturing to 10nm. The companies estimate they'll be able to produce 10nm products by 2016.
Intel is the world's largest semiconductor chipmaker. Samsung and Toshiba are the first- and second-largest makers of NAND flash memory. The three plan to form a consortium of 10 companies that make products in the semiconductor or related industries.
Intel and Samsung are already approaching atomic size with their lithography technique. Lithography is the process of creating cells and transistors in silicon that are used to store bits of data. Currently, the companies are producing 20nm-class flash chips storing either one, two or three bits per cell. A nanometer is a millionth of a millimeter. At 25nm, NAND flash circuitry is 3,000 times thinner than a strand of human hair.
While all three companies are likely to use the smaller lithography to make more dense NAND flash chips, Intel will likely use it to develop faster microprocessors, according to the Nikkei Daily.
The Nikkei news agency also said Japan's Ministry of Economy, Trade and Industry may fund up to half the project's cost, or roughly $61 million of the $122 million project, with the companies paying for the rest.
In July, Toshiba announced the start of construction on a new NAND flash chip fabrication facility (dubbed Fab 5) at its Yokkaichi City, Japan, operation.
NAND flash memory has been the single biggest change to drive technology in recent years, with the storage medium showing up in data centers, high-end laptops like Apple's MacBook Air and in memory cards in mobile devices. Apple has largely driven the adoption rate with its use of NAND flash in its popular iPods and iPhones, sales of which helped drive flash memory costs down through mass production.
iSuppli Corp. forecasts that the global flash memory card market will grow from 530 million units this year to 9.5 billion units by 2013, when it will be worth $26.5 billion. The market for high-capacity memory chips room to grow, according to iSuppli, largely because of the rise of smartphones. The more features they offer (whether it's touch screens, wireless Internet access or video capabilities) the more storage they need.
But for NAND flash to compete more with traditional hard disk drives, production costs must come down. By producing denser NAND flash chips, manufacturers can pack more capacity into the same space, thereby reducing the costs.
However, there are inherent problems with shrinking the size of circuitry used in semi-conductors, most notably an increase data error rates from electrons bleeding through ever-thinner silicon walls. That requires the development of more sophisticated error correction code (ECC).
Traditional ECC, however, requires code redundancy and data read latency as the number of errors that must be corrected goes up.
There are several materials being explored by memory manufacturers to alleviate the problem. One technology several nonvolatile memory companies are exploring is Resistive Random-Access Memory (RRAM). Instead of using silicon as a resistive material, RRAM uses a filament or conduction path in the silicon.
[Lucas Mearian covers storage, disaster recovery and business continuity, financial services infrastructure and health care IT for Computerworld. Follow Lucas on Twitter at @lucasmearian or subscribe to Lucas's RSS feed. His e-mail address is email@example.com.]
This story, "Intel, Toshiba, Samsung team to shrink chip circuitry" was originally published by Computerworld.