Intel’s next-generation platform for laptops will provide more visually stunning graphics and better power management features, the company said on Tuesday.
The company’s next mobile platform, code-named Calpella, will be released in 2009. It is a follow-up to Intel’s Centrino 2 mobile platform released last month, Intel officials said at the Intel Developer Forum in San Francisco.
Calpella will include chips based on Intel’s upcoming Nehalem microarchitecture, which is expected to reach consumers in the second half of 2009. Packing two and four cores, Nehalem-based laptop chips will be an upgrade from Intel’s current Core 2 chips, which are used in notebooks and desktops. Nehalem cuts bottlenecks from the Core microarchitecture to deliver better system speed and performance-per-watt.
Intel is integrating the memory controller and graphics core into the CPU for Nehalem-based laptops, which should boost system and graphics performance, according to the company. That should also reduce the need of integrated graphics capabilities, though gamers may need a discrete graphics card for high-end graphics performance.
Calpella will also feature better manageability and security features for business and home users, said Dadi Perlmutter, executive vice president at Intel, during a speech. Perlmutter did not provide further details about the platform, saying the company would detail it as the release date comes closer.
The first Nehalem chips will reach high-end desktops, said Pat Gelsinger, senior vice president at Intel, during a speech at the IDF. Intel’s first Nehalem chip has been branded Core i7 and will ship in the fourth quarter this year. The Nehalem-based server products, code-named Nehalem-EP, will go into production later this year, and will be followed up by another version, code-named Nehalem-EX, which will go into production in 2009.
With between two and eight cores, the speed of Nehalem chips will be enhanced with QuickPath Interconnect (QPI) technology, which integrates a memory controller and provides a faster pipe for chips and system components to communicate. Nehalem will support DDR3 memory and include shared 8M bytes of shared L3 cache for local cores to better execute threads. Each core will be able to execute two software threads simultaneously, so a server with eight processor cores could potentially run 16 threads simultaneously.
The new chips will also feature Turbo Mode technology, which improves power efficiency of the chips by disabling inactive cores to prevent power leakage.
“The key idea in power management is quite simple — to shut things off when not in use,” said Rajesh Kumar, an Intel fellow during a presentation at the forum.
This is an improvement from Intel’s earlier power-saving technology, which wasn’t efficient in dealing with power leakage from inactive cores, Kumar said. The Turbo Mode technology has been around for a decade but was hard to execute. It required the development of a whole new process technology to make the technology possible. Several sensors measure power in real time, and a new microcontroller has been included to work on power management, he said.
Processing power could also increase with the technology, Kumar said. All cores may not be needed to perform a given workload, so the technology reassigns power from inactive cores to boost performance of operational cores. The more power constrained you are, the more performance will increase, heye said.
Turbo Mode technology will be implemented in future chip architectures, Kumar said.