The HyperTransport Technology Consortium
— a non-profit organization of which Apple is a member — is making two major announcements this week as President Gabriele Sartori gives the keynote address at the Platform Conference in San Jose, California.
The Consortium has announced the formal release of 1.05 HyperTransport Technology I/O Link Specification. They will also announce a new HyperTransport Technology Compatibility Program designed to facilitate the industry-wide use of the HyperTransport chip-to-chip interconnect specification.
HyperTransport interconnect technology is a high-speed, high-performance, point-to-point link for integrated circuits, developed to enable the chips inside high-performance computers, networking and communications devices to communicate with each other faster than with existing technologies. HyperTransport technology’s bandwidth of 12.8GB/sec purportedly offers up to a 48-fold increase in data throughput, compared with existing system interconnects that typically provide bandwidth up to 266MB/sec. HyperTransport can also be built atop the existing PCI standard.
The new release of the 1.05 HyperTransport Technology I/O Link Specification defines several new HyperTransport technology features, including a new HyperTransport switch function, enhanced PCI-X 2.0 interworking support, increased concurrency and 64-bit addressing. The new specification extends the set of electrical and protocol definitions and enables a new class of HyperTransport-based products, according to Sartori.
“HyperTransport-enabled systems can now be easily expanded with low-latency HyperTransport switches and enabled to link to popular PCI-X 2.0 devices,” he explained.
PCI-X is an update to PCI technology that doubles the transfer speed. Version 2.0 will purportedly double and then quadruple the speed of PCI. PCI-X, just now arriving in today’s servers, can transfer 1.07 gigabytes of data per second, according to Roger Tipley, president of the PCI special-interest group that governs the specification, in a
article. PCI-X 2.0 pumps data faster for each tick of the clock, with the PCI-X 266 standard at 2.1 gigabytes per second and PCI-X 533 at 4.3 gigabytes per second.
PCI-X 2.0 will be good for connections to 10 gigabit-per-second Ethernet networks, high-speed hard disk controllers and forthcoming 10 gigabit-per-second Fibre Channel connections to storage networks, Tipley said.
The HyperTransport switch function enables the connection of virtually unlimited numbers of HyperTransport devices. What’s more, by switching traffic locally, the HyperTransport switch reduces latency and potential bandwidth logjams. The switch definition supports the concentration of multiple width buses that, in turn, allows system designers to apply just the right amount of bandwidth in a particular section of a design, according to Sartori.
The enhanced PCI-X 2.0 interworking features are designed to simplify the connection of HyperTransport-enabled systems to PCI-X 2.0 subsystems. Included are support for PCI-X 2.0 error indications and the ability to handle device configuration messages of up to 4Kbytes. This supports the 128byte burst message feature in PCI-X 2.0.
The HyperTransport Release 1.05 concurrency feature allows a system to have more than the previous 32 requests outstanding. This situation can occur in networking or server applications where a given data stream pipeline is “clogged” with outstanding requests that have not been fulfilled. This new feature eliminates this potential bottleneck in networking applications by allowing up to 128 outstanding requests.
The 64-bit addressing feature extends the original specification’s 40-bit address in order to support large address spaces needed. The feature is backward compatible with older address schemes, making the 64-bit address optional, and enabled on a link-by-link basis.
Meanwhile, the HyperTransport Technology Compatibility Program consists of a set of electrical and protocol checklists and a Device Under Test Connector definition that HyperTransport-enabled product manufacturers can use to help ensure compatibility between their devices. It gives users and designers a means of comparing HyperTransport-enabled devices with the goal of ensuring that products from one manufacturer will easily integrate with others, according to Sartori.
The HyperTransport Technology Compatibility Program is available to members of the HyperTransport Consortium online. Consortium members can use these checklists and the test connector definition to test their products against the various levels of specifications of the HyperTransport technology. The current specification release is 1.05.