announced its new HiPerMOS7 (Seventh Generation High Performance Metal Oxide Semiconductor — called HiP7) manufacturing process that will allow future processors from Motorola, including the next PowerPCs, to run faster, use less power, generate less heat and be less expensive than ever before. This new fabrication process will be the first to use 0.13-micron lithography and SOI (Silicon on Insulator) technology along with copper interconnects.
“With HiPerMOS7, Motorola has tried to implement parallel design efforts with all of Motorola’s future microprocessors,” said Suresh Venkatesan, Motorola’s HiP7 Process Technology Manager. “Initial products using SOI and HiP7 will address the embedded and infrastructure markets, with Motorola’s PowerPC microprocessors adopting these technologies early next year.” Motorola hopes that the smaller size of a processor manufactured with the new process will allow its embedded processors to drop significantly in price and increase in functionality. Venkatesan stresses that HiP7 will migrate to the PowerPC portfolio.
Currently, Motorola uses a 0.18-micron lithography process to manufacture Motorola 7450s, the G4s currently used in Apple’s highest end systems. By moving to a far smaller 0.13-micron lithography process, Motorola’s new processors will be able to use less energy per transistor, and have more transistors per processor. “Speed and dynamic power consumption are a function of voltage and frequency,” said Venkatesan. “All things remaining equal, a processor manufactured using the 0.13-micron fabrication process could see a 50 percent power savings over a similar processor made using a 0.18-micron fabrication process.”
That’s not all. Because of the lowered power consumption of processors manufactured with the new process, it will be possible for Motorola to ramp up its processor’s frequencies. This, coupled with Motorola’s SOI technology which allows individual transistors to operate more quickly and efficiently, should allow Motorola to reach the goals that it outlined at last summer’s Microprocessor Forum for its GHz+ G4 Apollo.
Mike Mendacino, Motorola’s SOI Technology Manager, said that future PowerPC processors created using the 0.13-micron manufacturing process could have larger on-die L2 caches. “With more transistors on a given area, one could logically conclude that we could add more cache if the processor’s performance and price worked out in a larger cache’s favor,” said Mendacino. He also suggested that, given Motorola’s history, a larger on-die cache is a logical progression in the PowerPC’s development.
Venkatesan also said that Motorola is skipping the 0.15-micron manufacturing process. This may result in Motorola leapfrogging their semiconductor competitors, many of whom have recently begun shipping processor products using a 0.15-micron lithography process — Nvidia’s GeForce3 being a high-profile example. Nevertheless, other major semiconductor manufacturers have announced their own twist of a 0.13-micron manufacturing process. For example, rival processor manufacturer Intel last week announced that it had successfully manufactured its first .13-micron processors on a larger wafer.
Motorola is currently sampling embedded processors fabricated using the 0.13-micron process, which it intends to begin shipping in volume in the second quarter of this year. Motorola also will be showing off its new technology at the Embedded systems conference this week in San Francisco.