Apple CEO Steve Jobs aptly described the design philosophy for the new Power Mac G5 systems unveiled Monday morning at the Worldwide Developer’s Conference keynote speech as chip, system, product.
Apple’s new chip, which they call the G5 and IBM calls the PowerPC 970, marks the beginning of a new era for Apple. The PowerPC 970 is the first modern PowerPC to embrace a 64-bit architecture.
“I’m actually even more impressed by the G5 that I thought I’d be,” Microprocessor Report Editor Peter Glaskowsky said. “2GHz is impressive. Individually, these chips are faster than a Pentium 4. And with two of them, that’s incredible. I really can’t argue with Apple’s argument that the G5 is the fastest desktop available now.”
The move to 64-bit processing marks a significant change and massive potential performance boost for the PowerPC, which has traditionally been a 32-bit processor architecture. The kicker is that applications and even Mac OS X itself must be at least recompiled and potentially revised to derive a performance boost from the wider datapath on the G5. Additionally, developers will need to figure out ways to use the G5’s ability to work with data arrays larger than 4GB.
“Developers don’t need to do much to realize the power of the chips with 32-bit applications,” Glaskowsky said. “Photoshop doesn’t need 64-bit anything to work because people never render 4GB images. That would be a billboard at high resolution.”
The 64-bit capability is what makes the G5 interesting. Glaskowsky said that developers could now start thinking about manipulating arrays of data that are larger than anything seen outside of the $10,000 plus workstation range.
Jobs said that the new Power Mac systems will not ship until August — interesting because developers have a golden opportunity to learn about the new processor architecture and take that information back to their respective workplaces to apply to their applications. Glaskowsky was disappointed to not hear more about how the G5 worked in this arena, but he believes that developers will be briefed about it under the non-disclosure umbrella at WWDC.
Unlike X86 processors, The PowerPC always had 64-bit processing in the back of the specification. So, it was relatively easy for the PowerPC 970 to seamlessly support 32-bit applications. At the Microprocessor Forum last year, analysts for Microprocessor Report said that the 970 did this by simply scaling back when 32-bit code was used from using 64-bit registers to 32-bit registers with a remapping scheme at little to no performance loss. Jobs said that 32-bit applications would run on the new processor with “no problem,” and, according to Apple, 32-bit portions of the OS and 32-bit applications run natively. Moreover, a developer at the keynote was able to recompile his code to run 64-bit native in 15 minutes.
The G4, manufactured by Motorola, runs at speeds of 1GHz, 1.25GHz and 1.42GHz. In Apple’s implementations, the 1GHz Power Mac has a single processor, and the 1.25GHz and 1.42GHz versions ship as dual processor machines. The Front Side Bus (FSB) of Apple’s previous G4 models was 133MHz for the 1GHz G4 and 167 MHz for the dual 1.25GHz and dual 1.42GHz models. This was actually slower than the system memory, and the L3 cache helped reduce the performance penalty from that. With the faster FSBs of the G5 Power Mac design, an L3 cash provides little performance benefit.
The Power Macs that Jobs introduced begin with a single 1.6GHz G5 at the low end, followed by a single 1.8GHz G5 model in the middle and a 2GHz dual processor Power Mac Model at the high end. The G5 is manufactured using IBM’s 0.13-micron 8 layer copper Silicon on Insulator process.
At the Microprocessor Forum last year, IBM targeted the PowerPC 970 for speeds between 1.4GHz and 1.8 GHz. Jobs’ announcement of a 2GHz system suggests that IBM is exceeding those estimates in volume significant enough for a higher speed release. Jobs also said that he expected to have a 3GHz G5 model with a year. At the Forum, IBM senior PowerPC processor architect Peter Sandon also said that the company expected to sample the 970 in the second quarter of this year and have product available in the second half of this year. Jobs’ announcement Monday also suggests that IBM is at least on schedule and possibly on the fast end.
The Power PC 970 is derived from IBM’s industry respected Power4 server chip. Compared with the G4, the 970 has a longer pipeline and no connectors for an external L3 cache. The 970 has a 64KB on-chip L1 instruction cache and a 32KB on chip L1 data cache. The chip also sports a 512KB on-chip L2 cache that uses ECC (Error Correction) memory.
The G5 contains a SIMD (Single Instruction Multiple Data) unit that is similar to Motorola’s AltiVec execution unit on the G4. Analysts at Microprocessor Report said that IBM’s unit is similar to Motorola’s, and that both use the same instruction set. Applications coded to take advantage of AltiVec will see a similar performance benefit on the PowerPC 970. Apps that are AltiVec enabled and 64-bit native will see performance gains again.
To use the PowerPC 970, Apple had to work with IBM to create a new memory controller. The new Power Macs will use 400MHz 128-bit DDR RAM. The 64-bit datapath of the 970 allows for the addition of more RAM. The latest G4 Power Macs support up to 2GB of RAM, but Power Macs built around the 970 can support four times as much, up to 8GB. The memory bandwidth of the new G5 systems has also skyrocketed from 2.7GB/sec on the previous G4 systems to 6.4 GB/sec on low end G5 systems to 8GB/sec on 2GHz systems. Additionally, the dual processor G5 Power Mac has a separate memory channel for each processor, netting a total memory bandwidth of 16GB/sec.
The faster front side busses on the G5 Power Macs, 800MHz (clock doubled) on the low end rising to a double 1000MHz FSB (clock doubled) on the dual 2GHz system essentially remove the need for a large L3 cache on Apple’s G5 models. Processor caches are used to minimize the performance loss experienced by processors waiting from data with slower memory systems. With this bottleneck removed from the Power Mac design, the L3 cache can go.
Glaskowsky said that there may be even better surprises for G5 users in the near future. IBM is moving from a its 0.13-micron, or 130 manometer fabrication process, to a 90 nanometer process. This change alone will take the current G5 die size of 118 square millimeters down to 60 square millimeters.
“118 square millimeters is around the optimum size for a processor,” Glaskowsky said. “Larger and the chips get too expensive and smaller the chips lose performance. By going to 90nm, IBM can go to a larger cache on the chip, maybe 1MB or 2MB, or add an L3 cache.”
Apple has also decided to implement HyperTransport, a dedicated, high speed bus implementation championed by AMD and several other top-tier semiconductor companies, for communications between other components on the motherboard. At the low end, the Power Mac G5 sports 3 33MHz 64-bit PCI slots similar to those in the G4. In the middle, the Power Mac G5 has one full-length 133MHz 64-bit PCI-X slot and 2 full-length 100MHz PCI-X slots. The 2GHz Power Mac G5 has three full-length 133MHz PCI-X slots.
“PCI-X and 8GB of memory are not academic notes,” said Glaskowsky. “These will translate into end-user performance.”
The AGP slot bandwidth has been upgraded from 4X on the previous G4 to 8X Pro, allowing for the full power of a GeForceFX 5200 or a Radeon 9600 Pro graphics card to be unleashed.
Another innovation that Apple embraced with the G5 model is Serial ATA. The previous G4 models used Parallel ATA, which uses a 64-wire wide ribbon cable. Serial ATA boosts the G5’s bandwidth to drives to 150MB/sec and also increases the number of channels from one shared channel hosting two devices to two independent channels, each hosting one device. Additionally, PC manufacturers have shown a preference for Seral ATA because the connectors and cables are far smaller, improving airflow within the case. Apple has specifically redesigned the G5 with an all aluminum case that the company claims dramatically improves airflow and reduces noise by up to 30dBa compared with the previous G4.
Glaskowsky is convinced that the G5 case is overdesigned, suggesting that Apple plans to quickly ramp up the performance of the G5 processors and many of the computer’s other systems. If Apple makes a smooth transition to 90nm, he expects Jobs’ 3GHz promises to be fulfilled. And the case can handle it without a redesign.
The G5 boasts many more connectors on the back and a few convenience connectors on the front. On the back are the three PCI-X slots, an ADC connector and a DVI connector. For wireless, all G5’s support AirPort Extreme and Bluetooth as options, and connectors for the antennas are at the back of the new case design. For audio, the G5 has an analog audio in/out at the back and a headphone jack on the front. There are also optical digital audio in/out connectors on the back of the G5 case. Rounding out the back of the case are two USB 2.0 connectors, one FireWire 400 connector, one FireWire 800 connector, a modem jack and the gigabit Ethernet port. For convenience a FireWire 400 connector and a USB 2.0 connector are also located on the front of the case.
The three G5 models are priced as follows: 1.6 GHz single G5, 800MHz FSB 256MB RAM and an 80GB hard drive for $1,999, 1.8GHz single G5, 900MHz FSB 512MB RAM and a 160GB hard drive $2,399, and 2GHz dual G5, dual channel 1000MHz FSB 512MB RAM and a 160GB hard rive for $2,999. All systems come with an Apple SuperDrive, Apple Pro Mouse and Keyboard, a DVI to VGA connector, a USB extension cable, modem cable and an AirPort antenna.