At the Microprocessor Forum in San Jose on Tuesday, IBM’s Power5 Chief Scientist Dr. Balaram Sinharoy divulged additional details about the chip he’s been working on for the past several years.
The Power5 is intended to build upon the Power4 design with enhancements made to improve performance, allow more processors to be used in a system and to improve power efficiency. At the same time, Sinharoy said that all code developed for the Power4 will be fully compatible with the Power5.
Like the Power4, the Power5 contains two processor cores on one chip. These cores share one 1.92 MB on-die L2 cache compared with a 1.44MB L2 on-die cache on the Power4. The Power4 and Power5 both have an off-chip L3 cache, but IBM designed the L3 cache to connect directly to the L2 cache instead of between the memory controller and the processor like on the Power4. Sinharoy said that this “backdoor” cache allows the Power5 to be more scalable with multiprocessor designs. The “backdoor” cache improves performance by reducing the L3 cache latency.
The Power5 also incorporates an on-die memory controller to improve performance and reliability. Each Power5 can support up to 1024GB of memory, compared with 512GB for each Power4. Since the memory controller is on the chip, designers need only to attach memory to the chip instead of going through a northbridge.
IBM will distribute the Power5 in a Multi-chip Module that is a 95mm by 95mm block of four Power5 chips with four 36MB off-chip L3 caches. Up to 16 of these Multi-chip Modules can be implemented together for a total of 128 logical processors. The arithmetic of that is two cores per Power5 processor, four processors per module and 16 modules. Sinharoy said that all that needs to be added to a Multi-chip Module to create a system was any I/O required and memory.
The Power4 collects a group of up to five instructions per clock cycle and can complete one group of instructions per clock cycle. The Power5 doubles that throughput by collecting two groups of up to five instructions per clock cycle and completing two groups per clock cycle. Sinharoy said that is was not uncommon to see a “40 percent improvement for SMT (Symmetric Multithreading) instructions,” a key performance characteristic for server processors, over the Power4.
While no specific Macintosh announcements were made, Sinharoy noted during his presentation that the PowerPC 970, the processor that drives Apple’s G5, was derived from the Power4 design, suggesting that such a step would be logical again as IBM engineers refine the Power5 design. The PowerPC 970 strips one processor core from the Power4 design and also includes several other connection and multiprocessing sacrifices to make the chip small and affordable enough for desktop use.
The Power5 design includes an improvement that may also be a nod at Apple. The Power5 adds a single thread performance mode that allows the processor to sacrifice some of its scalability to focus resources on completing a single thread. In layman’s terms, the Power5 can ease off on some of the characteristics that allow it to easily handle many different tasks at a time to focus on one application or task. Unlike server applications, desktop applications are rarely threaded.
For now, don’t expect the Power5 to be used outside of the commercial computing market. Even using a 0.13-micron copper SOI (Silicon On Insulator) manufacturing process, a single 276 million transistor Power5 chip measures 389 square millimeters—far larger than the 267 square millimeter Power4 and almost four times as large as a PowerPC 970.
IBM also added a power management scheme to the Power5 that Sinharoy claims will drastically reduce power consumption and heat generation. His presentation contained no information on the power needs or heat dissipation characteristics of the Power5.
Sinharoy said that the Power5 is working in IBM’s labs now and is on schedule to ship next year; however, he made no mention of benchmark performance or clock speed of the new processor. Sinharoy said that a Power5+, which will be similar to the Power5 but manufactured using a 90-nanometer process, is tentatively scheduled for 2005. Finally, Sinharoy said that a Power6 is “well underway” and scheduled for introduction in 2006.