Semiconductor makers will soon need to find a new substrate to replace the pure silicon wafers used to make chips if they are to keep pace with expected advances in chip-making technology, according to the head of a prominent industry group.
With each advance in manufacturing process technology, the semiconductor industry has improved its ability to produce chips that are cheaper, consume less power and offer better performance. But these advances are becoming more difficult to obtain as the geometry of chip designs gets ever smaller, according to Stanley Myers, president and chief executive officer of Semiconductor Equipment and Materials International (SEMI).
“The pure silicon substrate is reaching its limits,” Myers said earlier this week in Shanghai.
This isn’t the first time that the semiconductor industry has looked for ways to improve on the pure silicon wafer as a substrate. Presently, the most advanced process technology used to produce chips in commercial volumes is the 90 nanometer technology. Advances in process technology, such as the shift from 130 nm process technology to 90 nm, have shrunk the pathways on a chip that electrons follow, leaving less room for electrons to move between the molecules of a silicon wafer. The answer to this problem was strained silicon.
Strained silicon substrates overcome this challenge by distorting silicon crystals to increase the performance of a chip. At the molecular level, silicon crystals resemble a lattice of neatly arrayed molecules. Stretching — or straining — this lattice by introducing a thin layer of silicon-germanium alloy on the silicon wafer creates more room for the flow of electrons, allowing them to move with less resistance. This technique helps transistors to switch state faster, improving overall performance, and to lower power consumption.
Strained silicon works well with today’s most advanced processes and will continue to be used as a substrate with upcoming 65 nm and 45 nm processes, but a different substrate is required for more advanced processes, Myers said.
The problem is size. As process technology becomes more advanced, the distance that separates the features on a chip is reduced and leakage — the ability of electrons to freely move between different areas of the chip — is increased. Leakage wastes energy as heat and garbles the operations of a chip.
Finding a suitable substrate to use with future chip processes won’t be impossible but it will take time, creativity and lots of money, according to Myers. “It’s not a roadblock, but it’s a high brick wall to climb over,” he said.
While an answer to this problem has yet to be found, silicon will continue to form the basis of future chip substrates. However, new materials will have to be added to the silicon in order to obtain the insulating and conducting properties required to make future chips work properly. “Below 45 nm, you’ve got to begin thinking of a revolutionary change in the substrate,” Myers said.
Finding a replacement for pure silicon wafers isn’t the only problem facing the chip industry. Another challenge below 45 nm is cleaning the chip during the manufacturing process, Myers said. Van der Waals forces — the name given to a weak attraction between molecules — can bind undesirable molecules, such as boron, with silicon molecules. At the chip-feature sizes expected with technologies beyond the 45 nm process, this presents a serious problem that can’t be solved with existing methods, he said.
“This attraction between different molecules could wipe out a chip,” Myers said, noting that existing cleaning techniques, which use water or chemicals, are not capable of breaking the van der Waals forces.
Chip companies have several years to solve these problems before they start moving beyond the 45 nm process. Intel Corp., which is introduction of advanced process technology, plans to begin producing chips using a 65 nm process this year and will begin the shift to a 45 nm process in 2007, according to Tim Mohin, director of sustainable development at Intel. The company plans to begin using a 32 nm process in 2009 and will move to a 22 nm process in 2011, he said.
By then, there should be a solution. Myers expects that a suitable substrate could be available in five to six years, but chip companies will have to work together — and share the costs — to make this happen. “There needs to be more joint R&D (research and development) in materials,” he said.